1. Field of the Invention
This invention relates to an improved demodulator for use in communication systems employing a binary phase modulated carrier. More particularly, the invention relates to novel sampling apparatus which provides performance and cost advantages.
2. Description of the Prior Art
Coherent phase shift keyed digital modulation techniques are known to be especially suitable for electric utility power line carrier communication systems. The basic task of such systems is to transmit information over the primary and secondary distribution conductors between a central utility location and customer locations. The information may consist of remote meter reading commands, metering data, load shed commands, load status information, and various other data useful in automated distribution systems.
The data is converted at the transmitting end to strings of binary data bits in a predetermined message format. The data bits assume one of two possible states, typically referred to as "mark" and "space" or logic 1 and logic 0. The information, when converted to digital form, is referred to as baseband data.
In order to transmit the message from the source to the destination, the baseband data is modulated onto a carrier signal, generally of much higher frequency, through a coherent phase modulation technique by causing a 180.degree. phase shift of the carrier whenever the baseband data undergoes a transition between mark and space. The modulated carrier signal is then coupled to the power line conductor and propagated to the destination.
A power line communication system employing coherent phase shift keyed modulation is described in U.S. Pat. No. 4,311,964, issued Jan. 19, 1982 to John R. Boykin and assigned to the assignee of the present invention. In the transmitter, the bipolar data bits are phase encoded onto the carrier with identical bit intervals or data symbol times defining a predetermined data rate and are synchronized with the carrier signal so as to be integrally related to the carrier signal frequency. In the receiving apparatus disclosed therein, the modulated carrier is hard limited to produce square wave carrier signals. The polarity of the hard limited carrier signals is then sampled at equal intervals at a sampling pulse rate selected such that the ratio of the sampling rate and the carrier frequency is not an integer. The sampling process enables the demodulator to determine the relative position of the square wave carrier frequency zero crossings. This information is in turn used to derive the phase of the incoming carrier signal relative to an internally generated reference signal. From this information, the demodulator then determines when the phase of the carrier signal undergoes a 180.degree. shift and reconstructs the baseband digital data.
The period of the sampling signal in the demodulator of the aforementioned U.S. patent is normally set to N.+-.1/m cycles of the carrier frequency where N and M are integers. This generates an "image" of the received signal at a reduced frequency of: ##EQU1## where f.sub.c is the original carrier frequency. The baud rate B is then established by determining the number of cycles K of the image frequency per baseband data bit. Therefore, if K cycles of f.sub.i constitutes one baseband data bit period, then the baud rate is: EQU B=f.sub.c /K(N.times.m+1)
For example, a CPSK system having the values m=8, N=5, K=4 yields a baud rate of B=76.2195 for a carrier frequency f.sub.c =12.5 KHz.
It can be seen that in order to provide a reasonably high baud rate, the values of N, m, and K should be as small as possible. In a microprocessor controlled system, such constraint places a considerable demand on the controlling microprocessor, since it must be interrupted every N.+-.1/m cycles of carrier frequency to produce a sample pulse. For the above listed example with a carrier frequency of 12.5 KHz, an interrupt rate of 2.439 KHz is required.
Another characteristic of CPSK digital demodulators, such as described in the aforementioned patent, is a sensitivity to incoming signals having frequencies other than the desired carrier frequency. These additional frequencies to which the demodulator responds are called aliasing frequencies, and are the frequencies which produce the same image frequency for other valid denominators in the equation: ##EQU2## where N is constant. In the example given above: ##EQU3## Therefore, aliasing frequencies fa occur at: ##EQU4## and all solutions to the equation: EQU f.sub.a =12,500/41.times.(8.times.N.+-.1)
for integer values of N unequal to 5.
To a limited extent, the sensitivity to aliasing frequencies can be reduced by proper filtering techniques, but it has the effect of reducing the performance of the demodulator under high noise conditions. By increasing the sampling rate, it is possible to improve the performance of the demodulator to permit detection of a weaker carrier signal in the presence of high noise levels. However, increasing the sampling rate raises the interrupt rate for the microprocessor, and the point is rapidly reached where performance is limited by computing capabilities of the microprocessor. It would therefore be desirable to provide a CPSK digital demodulator having a higher effective sampling rate without increasing the processing demands of the microprocessor. Furthermore, it would be desirable to provide a digital demodulator having a reduced sensitivity to aliasing frequencies.